Dynamic random access memory (DRAM) devices provide the benefits of higher storage densities and less power consumption in comparison to other memory technologies, including and most notably, static random access memory (SRAM) devices. However, these benefits come at the cost of incurring various delays in accessing the memory cells making up a DRAM device, both at regular intervals, and in the time periods immediately before and after each access to either read data from the memory cells or to write data to the memory cells. The effect of these various delays has been to slow down the effective rate at which data stored within DRAM devices may be accessed, and although various ways have been devised in the prior art to mitigate the effect of these delays such that it is sometimes possible to entirely counteract certain delays in certain situations, the effect of these delays continues to be felt to a significant degree.
Common DRAM devices are made up of many memory cells organized into multiple banks of memory cells, with the memory cells inside of each bank being organized into an array of rows and columns. For data to be written to or read from one or more memory cells within a given row of a given bank, requires that the given row (also commonly referred to as a “page”) within the given bank be “opened” for access with a row activate command and a delay be incurred to allow the row activation to complete before the actual reading or writing of data can take place. Unfortunately, only one row of any bank may be open at a time, and if a row other than the given row is already open in the given bank, then that other row must be “closed” with a precharge command and a delay be incurred to allow the precharge to complete before the row activate command to open the given row can be transmitted.
The delay incurred to allow a precharge to finish closing one row before another can be opened in the same bank is a significant delay, and various schemes have been devised to attempt to counteract this delay.